The semiconductor integrated circuit (IC) industry has experienced exponential growth. Technological advances in IC materials and design have produced generations of ICs where each generation has smaller and more complex circuits than the previous generation. In the course of IC evolution, functional density (i.e., the number of interconnected devices per chip area) has generally increased while geometry size (i.e., the smallest component (or line) that can be created using a fabrication process) has decreased. This scaling down process generally provides benefits by increasing production efficiency and lowering associated costs. Such scaling down has also increased the complexity of processing and manufacturing ICs.
For example, reflectivity control has been a challenge for lithography. In a typical lithography process, a resist film is coated on a surface of a wafer and is subsequently exposed and developed to form a resist pattern. The resist pattern is then used for etching the wafer to form an IC. When the resist film is exposed with a radiation, it is important that reflection of the radiation by any resist under-layers be controlled. Otherwise, the reflection might negatively affect the resist pattern resolution. Reflection control is particularly troublesome when the wafer has high aspect ratio topography, such as complicated FinFET structures or other three-dimensional microstructures. One approach is to apply an anti-reflective coating (ARC) layer underneath the resist layer and use the ARC layer to absorb the radiation during exposure. The ARC layer is subsequently etched using the resist pattern as an etch mask, thereby exposing the wafer underneath for further processes. However, a typical ARC layer has low etching rate (high etching resistance). When the ARC layer is etched, the resist pattern is also considerably consumed, leading to undesirable resist pattern CD shrinkage and associated fabrication issues.